The present disclosure relates generally to semiconductor device manufacturing and, more particularly, to a process-robust alignment mark structure for semiconductor wafers.
The fabrication of integrated circuit (IC) devices on a semiconductor wafer involves a number of steps wherein patterns are transferred from photolithographic masks to the wafer. A masking step, for example, includes an etching step and defines selected areas to be exposed on the wafer for subsequent processes such as oxidation, metal deposition and impurity introduction. With IC device and feature sizes becoming increasingly smaller, it is important for a photolithographic mask to be aligned precisely with the wafer during the masking step in order to minimize any misalignment between the layers.
Most alignment schemes utilize alignment targets or marks that are defined on the wafer during a previous processing step. Typically, each alignment target includes topographical marks which may be formed by etching a plurality of xe2x80x9cstepsxe2x80x9d into the wafer. These steps may have, for example, a height of about 1,200 angstroms (xc3x85), with a width and spacing therebetween of about 10 microns (xcexcm). The alignment targets are used to diffract a laser alignment beam generated by a photolithography machine (commonly known as a wafer stepper) during the masking process. The diffraction pattern is received by the wafer stepper, and the relative position of the wafer and the photolithographic mask is thereafter adjusted accordingly so that the pattern of the photolithographic mask is transferred to the wafer in the precise location as desired.
Alignment marks created on wafer layers are often specifically designed with the particular processing step in mind in order to result in a sufficient contrast with the processed layer. For example, during the fabrication of the integrated circuit structures, a number of metallization layers are formed. Each of the metallization layers is typically separated from another metallization layer by an insulating layer therebetween. To provide an overlying metallization layer without discontinuities or other flaws, it is desirous to have an underlying surface for the metallization layer that is as flat or planar as possible. It has thus become commonplace to smooth the surface of a layer in preparation for a subsequently formed metallization layer by applying a planarization process. Certain planarization techniques, such as chemical-mechanical polishing (CMP), often result in a dishing or indentation of the wafer surface. Accordingly, alignment marks to be formed in metallization layers may include small segmented patterns of a uniform dimension so that dishing does not affect the integrity of the mark. A particular segment dimension may even be determined experimentally or by trial and error prior to incorporating the mark design into the wafer.
Unfortunately, process variations can also impact the contrast of an alignment mark. For example, a variation in the degree of CMP dishing, or perhaps a variation in the amount of applied chemical vapor deposition (CVD) metal fill, might make a mark more or less visible with regard to the particular imaging method of the wafer stepper. The variations may be from wafer to wafer and lot to lot. Furthermore, a change in process can result in the necessity for new alignment mark design and/or new reticle manufacture, along with the increased costs associated therewith. It is desirable, therefore, to provide an alignment mark structure with reduced susceptibility to process variability which might otherwise result in rework or other adverse effects upon the IC chip function.
The above discussed and other drawbacks and deficiencies of the prior art are overcome or alleviated by an alignment mark structure for use upon a semiconductor substrate. In an exemplary embodiment, the alignment mark structure includes a plurality of segments arranged in an alignment pattern, with each of the plurality of segments being formed from a base pattern created on the substrate. The base pattern includes a plurality of sizes, wherein each of the plurality of sizes of the base pattern is repeated throughout an entire length of each of the plurality of segments.
In one aspect, the base pattern is a square pattern wherein individual squares within the base pattern are arranged into rows and columns, with each square being situated proximate another square having a different size, along a horizontal and vertical direction. The individual squares may be formed as raised surfaces on the semiconductor substrate or, alternatively, as depressions within the semiconductor substrate. In an alternative embodiment, the base pattern is an elongated diagonal.